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128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O
Specification of 128M (8Mx16bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 /Aug. 2009 1
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No. 0.1 0.2 Initial Draft - Define IDD specification -. Correct Temp range(p.9 & p.10) -. Modify IDD Values(p.11 & p.12) -. Omit a typo in a package inforamtion -. Modify package information(add tolerance) History Draft Date Sep. 2007 Feb. 2008 Remark Preliminary Preliminary
1.0
Jun. 2008
1.1 1.2
Jul. 2009 Aug. 2009
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
DESCRIPTION
The Hynix H55S1262EFP is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix 128M Mobile SDRAM is 134,217,728-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 2,097,152x16. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randonaccess operation. Read and write accesses to the Hynix Mobile SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array, half array, quarter array Temperature Compensated Self Refresh of 45 or 85 degrees oC. The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically adjust refresh rate according to temperature without external EMRS command. Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. All inputs are LV-CMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
INFORMATION for Hynix KNOWN GOOD DIE
With the advent of Mullti-Chip package (MCPs), Package on Package (PoP) and system in a package (SiP) applications, customer demand for Known Good Die (KGD) has increased. Requirements for smaller form factors and higher memory densities are fueling the need for Wafer-level memory solutions due to their superior flexibility. Hynix Known Good Die (KGD) products can be used in packaging technologies such as systems-in-a-package (SIPs) and multi-chip packages (MCPs) to reduce the board area required, making them ideal for handheld PCs, and many other portable digital applications.
Hynix Mobile DRAM will be able to containue its constant effort of enabling the Advanced package products of all application customers. - Please Contact Hynix Office for Hynix KGD product availability and informations.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
FEATURES
Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed Power Supply Voltage : VDD / VDDQ = 1.7V to 1.95V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Programmable burst length: 1, 2, 4, 8 or full page Programmable Burst Type : sequential or interleaved Programmable CAS latency of 3 or 2 Programmable Drive Strength Low Power Features - Programmable PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - Programmable DS (Drive Strength) - Deep Power Down Mode -25oC ~ 85oC or -30oC ~ 85oC Operation Temperature - Extended Temp. : -25oC ~ 85oC - Mobile Temp. : -30oC ~ 85oC
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Package Type : 54Ball FBGA
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
128Mb Mobile SDR SDRAM ORDERING INFORMATION
Part Number H55S1262EFP-60E H55S1262EFP-75E H55S1262EFP-A3E H55S1262EFP-60M H55S1262EFP-75M H55S1262EFP-A3M Clock Frequency 166MHz 133MHz 105MHz 166MHz 133MHz 105MHz CAS Operation Organization Interface Latency temperature 3 3 3 3 3 3 4banks x 2Mb x 16 LVCMOS Mobile Temp (-30oC ~ 85oC) 54 ball FBGA 4banks x 2Mb x 16 LVCMOS Extended Temp (-25oC ~ 85oC) 54 ball FBGA Package
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BALL DESCRIPTION
1 A B C D E F G H J
VSS DQ14 DQ12
2
DQ15 DQ13
3
VSSQ VDDQ
4
6
7
VDDQ VSSQ
8
DQ0 DQ2
9
VDD DQ1
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
NC
VSS
TOP VIEW
VDD
LDQM
DQ7
UDQM
CLK
CKE
/CAS
/RAS
/WE
NC
A11
A9
BA0
BA1
/CS
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
Top view
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
BALL DESCRIPTION
SYMBOL CLK CKE CS BA0, BA1 A0 ~ A11 RAS, CAS, WE UDQM, LDQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC TYPE INPUT INPUT INPUT INPUT INPUT INPUT INPUT I/O SUPPLY SUPPLY DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will be one of the states among (deep) power down, suspend or self refresh Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM Bank Address : Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 Command Inputs : RAS, CAS and WE define the operation Refer function truth table for details Data Mask : Controls output buffers in read mode and masks input data in write mode Data Input/Output : Multiplexed data input/output pin Power supply for internal circuits Power supply for output buffers No connection
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ABSOLUTE MAXIMUM RATING
Parameter Case Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time
Note1 - Extended Temp. : -25oC ~ 85oC - Mobile Temp. : -30oC ~ 85oC
Symbol TC TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER
Rating -25 ~ 85 1) -30 ~ 85 1) -55 ~ 125 -1.0 ~ 2.6 -1.0 ~ 2.6 -1.0 ~ 2.6 50 1 260 . 20
Unit
oC
C V V V mA W
o
o
C . Sec
DC OPERATING CONDITION (TC= -25 to 85oC3)
Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD VDDQ VIH VIL
or -30 to 85oC 3) )
Min 1.7 1.7 0.8*VDDQ -0.3
Typ 1.8 1.8
-
Max 1.95 1.95 VDDQ+0.3 0.3
Unit V V V V
Note 1 1, 2 1, 2 1, 2
Note : 1. All Voltages are referenced to VSS = 0V 2. VDDQ must not exceed the level of VDD 3. - Extended Temp. : -25oC ~ 85oC - Mobile Temp. : -30oC ~ 85oC
AC OPERATING TEST CONDITION (TC= -25 to 85oC1)
Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement
Note1 - Extended Temp. : -25oC ~ 85oC - Mobile Temp. : -30oC ~ 85oC
or -30 to 85oC 1), VDD = 1.7V min to 1.95V max, VSS = 0V)
Symbol VIH / VIL Vtrip tR / tF Voutref CL
Value 0.9*VDDQ/0.2 0.5*VDDQ 1 0.5*VDDQ 30
Unit V V ns V pF
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
CAPACITANCE (TC= 25 oC, f=1MHz)
6/H/S Parameter Pin CLK Input capacitance Data input/output capacitance A0~A11, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM DQ0 ~ DQ15 Symbol Min CI1 CI2 CI/O TBD TBD TBD Max TBD TBD TBD pF pF pF Unit
DC CHARACTERRISTICS I (TC= -25 to 85oC5)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Note :
or -30 to 85oC 5))
Symbol ILI ILO VOH VOL
Min -1 -1 VDDQ-0.2 -
Max 1 1 0.2
Unit uA uA V V
Note 1 2 3 4
1. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V. 2. DOUT is disabled. VOUT= 0 to 1.95V. 3. IOUT = - 0.1mA 4. IOUT = + 0.1mA 5. - Extended Temp. : -25oC ~ 85oC - Mobile Temp. : -30oC ~ 85oC
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
DC CHARACTERISTICS II (TC= -25 to 85oC4)
Parameter Symbol
or -30 to 85oC 4), VDD = 1.7V min to 1.95V max, VSS = 0V)
Speed Test Condition 166MHz 133MHz Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRFC tRFC(min), CKE 0.2V See p.49~50 55 80 See Next Page 10 45 0.3 0.3 40 mA mA mA 1 Unit Note
IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS
5 mA 3 2 mA 1.2
IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current Standby Current in Deep Power Down Mode
Note :
10 mA 5 50 mA mA uA uA 2 3 1
IDD4 IDD5 IDD6 IDD7
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. See the tables of next page for more specific IDD6 current values. 3. Please contact Hynix office for more information and ability for DPD operation. Deep Power Down operation is a hynix optional function. 4. - Extended Temp. : -25oC ~ 85oC - Mobile Temp. : -30oC ~ 85oC
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
DC CHARACTERISTICS III
Temp. ( oC) 45 85 Memory Array 4 Banks 135 250 2 Banks 125 185 1 Bank 120 170 Unit
uA uA
Notes: 1. VDD / VDDQ = 1.7V min to 1.95V max 2. Related numerical values in this 45oC are examples for reference sample value only. 3. With a on-chip temperature sensor of Mobile memory, auto temperature compensated self refresh will automatically adjust the interval of self-refresh operation according to ambient temperature variations.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
166MHz Parameter System Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width CAS Latency=3 Access Time From Clock CAS Latency=2 Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time CAS Latency=3 CAS Latency=2 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 2.6 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 1.0 6.0 5.4 6.0 2.6 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 1.0 8.0 6.0 8.0 2.6 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 1.0 10 7.0 10 ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 3 1 1 1 1 1 1 1 1 CAS Latency=3 CAS Latency=2 Symbol Min tCK3 tCK2 tCHW tCLW tAC3 6.0 12 2.0 2.0 Max 1000 1000 5.4 Min 7.5 12 2.5 2.5 Max 1000 1000 6.0 Min 9.5 15 3.0 3.0 Max 1000 1000 7.0 ns ns ns ns ns 1 1 2, 3 133MHz 105MHz Unit Note
Note : Condition - [TC= -30 to 85 oC, VDD = 1.7V min to 1.95V max, VSS = 0V] 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. 3. Output Load : 30pF+No termination AC high level input voltage / low level input voltage : 1.6 / 0.2V Input timing measurement reference level : 0.9V Transition time (input rise and fall time) : 0.5ns
Output Load
Input
Output
Output timing measurement reference level : 0.9V Output load : CL = 30pF
Output
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CLK
30pF

Z = 50
tCK tCH 1.6V 0.9V 0.2V tSETUP 1.6V 0.9V 0.2V tHOLD tCL
tAC tOH
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
166MHz Parameter RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay AUTO REFRESH Period CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output CAS Latency=3 High-Z CAS Latency=2 Power Down Exit Time Self Refresh Exit Time Refresh Time Symbol Min tRC tRCD tRAS tRP tRRD tRFC tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tXSR tREF 2 0 2 3 2 1CLK + tCKS 120 64 60 18 50 18 12 80 1 0 2 Max 100K Min 72.5 22.5 50 22.5 15 80 1 0 2 Max 100K Min 90 28.5 60 28.5 19 80 1 0 2 Max 100K ns ns ns ns ns ns CLK CLK CLK 133MHz 105MHz Unit Note
tDPL+tRP 2 0 2 3 2 1CLK + tCKS 120 64 2 0 2 3 2 1CLK + tCKS 120 64 CLK CLK CLK CLK CLK CLK ns ms
Note : Condition - [TC= -25 to 85 oC or -30 to 85 oC, VDD = 1.7V min to 1.95V max, VSS = 0V] - Extended Temp. : -25oC ~ 85oC - Mobile Temp. : -30oC ~ 85oC
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Mobile Synchronous DRAM
PASR Extended Mode Register Self refresh logic & timer
Internal Row Counter
CLK CKE /CS /RAS /CAS /WE LDQM, UDQM State Machine Row Active
Row Pre Decoder
2Mx16 Bank3 2Mx16 Bank2 2Mx16 Bank1 2Mx16 Bank0 Row decoders Row decoders
DQ0
Row decoders
Sense AMP & I/O Gate
Output Buffer & Logic
Refresh
Memory Cell Array
16
16
Column Active
Column Pre Decoder
DQ15
Column decoders
Bank Select A0 A1 Address Register Address Buffers
Column Add Counter
Burst Counter Burst Length
A11 BA1 BA0
Mode Register
CAS Latency
Data Out Control
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 0 BA0 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0
OP Code
A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write
Burst Type
A3 0 1 Burst Type Sequential Interleave
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
Burst Length
Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
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BASIC FUNCTIONAL DESCRIPTION (Continued)
Extended Mode Register
BA1 1 BA0 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 DS A5 A4 0 A3 0 A2 A1 PASR A0
DS (Driver Strength)
A6 0 0 1 1 A5 0 1 0 1 Driver Strength Full 1/2 Strength 1/4 Strength Reserved
PASR (Partial Array Self Refresh)
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Self Refresh Coverage All Banks Half of Total Bank (BA1=0 or Bank 0,1) Quarter of Total Bank (BA1=BA0=0 or Bank 0) Reserved Reserved Half of Bank 0(Bank 0 and Row Address MSB=0) Quarter of Bank 0(Bank 0 and Row Address 2 MSBs=0) Reserved
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COMMAND TRUTH TABLE
Function Mode Register Set Extended Mode Register Set No Operation Device Deselect Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst stop Data Write/Output Enable Data Mask/Output Disable Auto Refresh Self Refresh Entry Self Refresh Exit Precharge Power Down Entry Precharge Power Down Exit Clock Suspend Entry Clock Suspend Exit Deep Power Down Entry Deep Power Down Exit CKEn-1
H H H H H H H H H H H H H H H H L
CKEn
X X X X X X X X X X X X X X H L H
CS
L L L H L L L L L L L L
RAS
L L H X L H H H H L L H X X
CAS
L L H X H L L L L H H H
WE
L L H X H H H L L L L L
DQM
X X X X X
ADDR
A10 /AP
BA
Note
2 2
Op Code Op Code X X Row Address Column L H L H H L X X X X X X V V V V V X V
X X X X X X X V
Column Column Column X X
L L H L H L H L H L
L L X H X H X H X V X
L L X H X H X H X V
H H X H X H X H X V
X X X
1
H
L
X
X
L
H
X
X
H L H L
L H L H
X X
X X X X
L
H X
H
L
X X
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
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CURRENT STATE TRUTH TABLE (Sheet 1 of 4)
Command Current State CS RAS CAS WE L L L L Idle L L L H L L L L Row Active L L L H L L L Read L L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 Action Amax-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : optional AP(A10=H) Start Read : optional AP(A10=H) No Operation No Operation ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst 4 8,9 8 13,14 13 4 4 3 3 13,14 13 7 4 6 6 14 5 Notes
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CURRENT STATE TRUTH TABLE (Sheet 2 of 4)
Command Current State Read CS RAS CAS WE H L L L L Write L L L H L L L Read with Auto Precharge L L L L H L L L Write with Auto Precharge L L L L H H H H X L L L L H H H X L L L L H H H X L L H X L L H H L L H X L L H H L L H X L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X BA BA X X X L L L L X L L H H X L H L H X BA BA BA0/ BA1 X Action Amax-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Continue the Burst ILLEGAL 13,14 13 10 4 8 8,9 Notes
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst Continue the Burst ILLEGAL
13,14 13 4,12 4,12 12 12
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL
13,14 13 4,12 4,12 12 12
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst
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CURRENT STATE TRUTH TABLE (Sheet 3 of 4)
Command Current State CS RAS CAS WE L L L L Precharging L L L H L L L L Row Activating L L L H L L L L Write Recovering L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 Action Amax-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set ILLEGAL 13,14 13 Notes
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP No Operation: Bank(s) idle after tRP ILLEGAL
4,12 4,12 4,12
13,14 13 4,12 4,11,1 2 4,12 4,12
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Row Active after tRCD No Operation: Row Active after tRCD ILLEGAL
13,14 13 4,13 4,12
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation ILLEGAL ILLEGAL Start Write: Optional AP(A10=H) Start Read: Optional AP(A10=H) No Operation: Row Active after tDPL
9
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
CURRENT STATE TRUTH TABLE (Sheet 4 of 4)
Command Current State Write Recovering CS RAS CAS WE H L L L Write Recovering with Auto Precharge L L L L H L L L L Refreshing L L L H L L L L Mode Register Accessing L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X Action Amax-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set No Operation: Row Active after tDPL ILLEGAL 13,14 13 4,13 4,12 4,12 4,9,12 Notes
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Precharge after tDPL No Operation: Precharge after tDPL ILLEGAL
13,14 13 13 13 13 13
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after tRC No Operation: idle after tRC ILLEGAL
13,14 13 13 13 13 13
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after 2 clock cycles No Operation: idle after 2 clock cycles
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 1)
Current State CKE Previous Current Cycle Cycle H L L L L L L H L Power Down L H L X H H H H H L X H CS X H L L L L X X H L RAS X X H H H L X X X H L X X L H Deep Power Down L L L X H L X X X X X X X X Command CAS X X H H L X X X X H X L X X X X X WE X X H L X X X X X H X X L X X X X BA0, AmaxBA1 A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Maintain Power Down Mode INVALID Deep Power Down mode exit Maintain Deep Power Down Mode 1 5 ILLEGAL 2 INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle 1 2 Action Notes 1 2 2 2 2 2
Self Refresh
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)
Current State CKE Previous Current Cycle Cycle H H H H All Banks Idle H H H H H H L H Any State other than listed above H H H H H L L L L L X H CS H L L L L H L L L L X X RAS X H L L L X H L L L X X Command CAS X X H L L X X H L L X X WE X X X H L X X X H L X X X X X X BA0, AmaxBA1 A0 Action Notes 3 3 3
Refer to the idle State section of the Current State Truth Table Auto Refresh Mode Register Set Refer to the idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
OP CODE
4 3 3 3 4
OP CODE X X X X
4
H L L
L H L
X X X
X X X
X X X
X X X
X X X
X X X
Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Mobile SDR SDRAM OPERATION State Diagram
Power On
ACT : Active
DPDSX
Precharge All Bank
FA RE
Auto Refresh
DPDS : Enter Deep Power-Down DPDSX : Exit Deep PowerDownEMRS EMRS : Ext. Mode Reg. Set MRS : Mode Register Set PRE : Precharge
(EXTENDED) Mode Register Set
(E)MRS
REFS
IDLE
REFX
E CK igh H
DS DP
Self Refresh
DEEP POWER DOWN READA SUSPEND
E CK igh H
E CK w Lo
Power Down
PREALL : Precharge All Banks REFA : Auto Refresh REFS : Enter Self Refresh REFSX : Exit Self Refresh READ : Read w/o Auto Precharge
Active Power Down
ow CK EH
C Lo KE w
WRITEA SUSPEND
C Hi KE gh
ACT
CK EL
Read Read
W
RI T
EA
C Lo KE w
E CK w Lo
READ SUSPEND
E PR
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E CK w Lo
READ with AP
A AD RE
WRITE with AP
igh
Write
READ
ROW ACTIVE
Write
WRITE
E CK igh H
READA : Read with Auto Precharge WRITE : Write w/o Auto Precharge WRITEA : Write with Auto Precharge
C H i KE gh
WRITE SUSPEND
PR E
PRE
Automatic Sequence Manual input
Precharge All
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
DESELECT
The DESELECT function (CS = High) prevents new commands from being executed by the Mobile SDRAM, the Mobile SDRAM ignore command input at the clock. However, the internal status is held. The Mobile SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command is used to perform a NOP to a Mobile SDRAM that is selected (CS = Low, RAS = CAS = WE = High). This command is not an execution command. However, the internal operations continue. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. (see to next figure)
ACTIVE
The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of the BA0,BA1 inputs selects the bank, and the address provided on A0-A12(or the highest address bit) selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. (see to next figure)
CLK CKE
High
CLK CKE
High
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0~Aamx BA0,1
A0~Amax
Row Address
RA
BA0,1
Bank Address Don't Care
BA
Don't Care
NOP command
ACTIVATING A SPECIFIC ROW IN A SPECIFIC BANK
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
READ / WRITE COMMAND
Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input. The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued. The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank and address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access.
CLK CKE
High
CLK CKE
High
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0 ~ A7
CA
A0 ~ A7
CA
A10 BA0,1
High to Enable Auto Precharge
A10
BA
Low to Disable Auto Precharge BA0,1
BA
Read Com m and O peration
D on't Care
W rite Com m and O peration
READ / WRITE COMMAND
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
READ
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The /CAS latency and burst length must be specified at the mode register.
tCK
CLK
Command
REA D
NOP tLZ
NOP tOH Do0 tAC Do1 Do2 Do3
DQ
CL = 2 REA D
Command
NOP
NOP tLZ
NOP tOH Do0 tAC Do1 Do2 Do3
DQ
CL = 3
Undefined
Don't Care
Read Burst Showing CAS Latency
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
READ to READ
Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
CLK Command
READ
NOP
READ'
NOP
Address
BA, Col
BA, Col
a
CL =2
b
DQ CL =3 DQ
Doa0
Doa1
Dob0
Dob1
Doa0
Doa1 Don't Care
Dob0
Consecutive Read Bursts
A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are shown in Figure. Full-speed random read accesses within a page or pages can be performed as shown in Fig.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
CLK Command READ READ
Address
BA, Col
BA, Col
n
CL =2
b
DQ CL =3
Don
Dob
DQ
Don
Dob Don't Care
1) Don (or b): Data out from column n 2) BA, Col n (b) = Bank A, Column n (b) 3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following Do n (b)
Non-Consective Read Bursts
CLK Command READ READ READ READ
Address
BA, Col
BA, Col
BA, Col
BA, Col
n
CL =2
x
b
g
DQ CL =3 DQ
Don
Don'
Dox
Dox'
Dob
Dob'
Dog
Dog'
Don
Don'
Dox
Dox'
Dob
Dob'
Dog
Dog'
1) Don, etc: Data out from column n, etc n', x', etc : Data Out elements, accoding to the programmd burst order 2) BA, Col n = Bank A, Column n 3) Burst Length = 1, 2, 4, 8 or full page in cases shown 4) Read are to active row in any banks
Don't Care
Randum Read Bursts
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
READ BURST TERMINATE
Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ command where X equals the desired data-out element.
CLK Com m and READ BURST
Address
BA, Col
n
CL =2
DQ CL =3 DQ
Don
Don'
Don
Don' Don't Care
1) Don : Data out from column n 2) BA, Col n = Bank A, Column n 3) Cases shown are bursts of 4, 8, or full page terminated after 2 data elem ents
Terminating a Read Burst
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
READ to WRITE
Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in next fig.
CLK Com m and READ BURST W RITE
Address
BA, Col
BA, Col
n
CL = 2
b
DQ CL = 3 DQ
Don
Don'
DIb0
D Ib1
DIb2
DIb3
D on
D on'
DIb0
DIb1
D Ib2
D Ib3
1) D O n = D ata Out from colum n n; DI b = D ata In to colum n b
D on't Care
Read to Write
Note : 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High so that the output buffer becomes High-Z before data input. 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data input.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
READ to PRECHARGE
Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGEcommand is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
CLK Com m and R EAD PRE tRP Address BA, Col ACT
n
CL = 2
Bank A, All
BA,
Row
DQ CL = 3 DQ
D on
D on D on't Care
1) D O n = D ata O ut from colum n n 2) Note that Precharge m ay not be issued before tRAS ns after the AC TIVE com m and for applicable banks. 3) The ACTIVE com m and m ay be applied if tRC has been m et.
READ to PRECHARGE
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Write
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory; if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. During WRITE bursts, the first valild data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. A full-page burst will continue until terminated. Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command.
CLK Command WRITE
Address
BA, Col
b
DQ DQ DQ DQ
DIb0 DIb0 DIb0 DIb0 DIb1 DIb1 DIb1 DIb2 DIb2 DIb3 DIb3 DIb4 DIb5 DIb6 DIb7
BL = 1 BL = 2 BL = 4 BL = 8
CL = 2 or 3
Basic Write timing parameters for
Don't Care
Write Burst Operation
Note : 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority. 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
WRITE to WRITE
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command. The first data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of desired data-in element.
CLK Command WRITE WRITE
Address DQ
BA, Col
BA, Col
b
DIb0 DIb1 DIb2 DIb3
n
DIn0 DIn1 DIn2 DIn3
DM
CL = 2 or 3
Don't Care
Concatenated Write Bursts
CLK Com m and W RITE W RITE W RITE W RITE W RITE N OP
Address
BA, Col
BA, Col
BA, Col
BA, Col
BA, Col
b
DIb DIb'
x
DIx DIx'
n
D In DIn'
a
DIa D Ia'
g
DIg DIg'
DQ
DM
CL = 2 or 3
D on't Care
Random Write Cycles
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
WRITE to READ
CLK Command WRITE READ
Address
BA, Col
BA, Col
b
DIb0 DIb1
n
DOn0 DOn1 DOn2 DOn3 CL = 2 BL = 4
DQ DQ DIb0 DIb1 DOn0 DOn1 DOn2 DOn3 CL = 3 BL = 4 Don't Care
The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency. The preceding write operation (WRIT) writes only the data input before the read command. The data bus must go into a high-impedance state at least one cycle before output of the latest data.
Note: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed. 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto Precharge was not activated). When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig.
CLK Command WRITE PRE
Address
BA, Col
b
DIb0 CL = 2 or 3 tDPL BL = 4
DQ
DIb1
DIOb2
DIb3
Non-Interrupting Write to Precharge
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure. Note that only data-inthat are registered prior to the tDPL period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
CLK Command WRITE PRE
Address
BA, Col
b
DIb0 DIb1 DIOb2 tDPL CL = 2 or 3 BL = 4
DQ
Interrupting Write to Precharge
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with autoprecharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this datasheet. Note the BURST TERMINATE command is not bank specific. Also, this command can be used to terminate the write bursts.
CLK CKE
High
CS
RAS
CAS
WE
A0 ~ Amax
Don't Care
BA0, 1
BURST TERMINATE COMMAND
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. Another command to the same bank (or banks) being precharged must not be issued until the precharge time (tRP) is completed. If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged, A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.
CKE
High A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write command, autoprecharge function is enabled. While A10 = Low, autoprecharge function is disabled. Don't Care
CS
RAS
CAS
WE
A0~Amax
A10 BA0,1
Bank Address
BA
PRECHARGE command
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write command. This precharges the bank/row after the Read or Write burst is complete. Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
AUTO REFRESH AND SELF REFRESH
Mobile SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode: AUTO REFRESH. This command is used during normal operation of the Mobile SDRAM. It is non persistent, so must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile SDRAM requires AUTO REFRESH commands at an average periodic interval of tREF. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile SDRMA, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*tREF.
The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recommended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section. The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these two modes.
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-
-SELF REFRESH. This state retains data in the Mobile SDRAM, even if the rest of the system is powered down. Note refresh interval timing while in Self Refresh mode is scheduled internally in the Mobile SDRAM and may vary and may not meet tREF time. After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF (max.) period on the condition 1 and 2 below. 1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting from self-refresh mode.
Note: tREF (max.) / refresh cycles.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
CLK CKE
High
CLK CKE
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0 ~ Amax
Don't Care
A0 ~ Amax
Don't Care
BA0, 1
BA0, 1
AUTO REFRESH COMMAND
SELF REFRESH ENTRY COMMAND
Note 1: If all banks are in the idle status and CKE is inactive (low level), the self refresh mode is set.
Function
Auto Refresh Self Refresh Entry
CKEn-1
H H
CKEn
H L
CS
L L
RAS
L L
CAS
L L
WE
H H
DQM
X X
ADDR
A10/AP
X X
BA
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
MODE REGISTER SET
The mode registers are loaded via the address bits. BA0 and BA1 are used to select between the Mode Register and the Extended Mode Register. See the Mode Register description in the register definition section. The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met.
CLK CKE
H igh
CS
RAS
CAS
WE
A 0 ~ Am ax
Cod e Cod e
MODE REGISTER SET COMMAND
D on 't C are
BA0, 1
Note: BA0=BA1=Low loads the Mode Register, whereas BA0=Low and BA1=High loads the Extended Mode Register.
CLK
Command
MRS
NOP
tMRD
Valid
Address
Code
Valid
Don't Care
Code = Mode Register / Extended Mode Register selection (BA0, BA1) and op-code (A0 - An)
tMRD DEFINITION
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
POWER DOWN
Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in progress. If power down occurs when all banks are idle, it is Precharge Power Down. If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is exited by setting CKE high while issuing a Device Deselect or NOP command. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby.
DEEP POWER-DOWN
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the Mobile SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Next Figure, DEEP POWER-DOWN COMMAND shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this state, CKE must be held in a constant low state. To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least 200 us. After 200 us a complete re-initialization routing is required defined for the initialization sequence.
CLK CKE
CLK CKE
CS RAS
CS RAS
CAS
CAS
WE
WE A0 ~ Amax BA0, 1 Don't Care Don't Care
A0 ~ Amax
BA0, 1
POWER-DOWN COMMAND
DEEP POWER-DOWN COMMAND
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
CLK
CKE
COMMAND All banks idle
NOP
NOP
ACTIVE tRCD
Input buffers gated off Enter power-down mode. Exit power-down mode.
tRAS tRC DON'T CARE
CLK
CKE tCKS COMMAND PCG NOP BST Input buffers gated off Pre-charge all Deep Power down entry tCKS NOP 200us(min) APCG
Deep Power down Exit DON'T CARE
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
CLK
tCKS tCKS tCKS tCKS
CKE
Power down Exit Time
CS RAS CAS
WE Ra
VDDR
Ca
BA0, BA1 Ra
Hi-Z
AP
DQ DQM
Qa0
Qa1
Qa2
Row Active Precharge Power down Entry Precharge Power down Exit Active Power down Entry
Read Active Power down Exit
Precharge Don't care
Note : CKE should be set high at least 1CLK + tCKS prior to Row active command.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
tCK
CLK
tCH
tCL
tCKS
tCKH
tCKS
tRAS(MIN)
CKE
tCMS
tCMH NOP AUTO REFRESH NOP or COMMAND INHIBIT Any COM
COMMAND
PRECHARGE
DQM
A0A9,Amax
ALL BANKS
A10
SINGLE BANK tAS tAH
BA0, BA1
BANKS
DQ
High-Z
Precharge all active banks
tRP
Enter self refresh mode
tXSR Exit self refresh mode (Restart refresh time base)
DON'T CARE
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Power-up and Initialization
Like a Synchronous DRAM, Low Power SDRAM(Mobile SDRAM) must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR). The following these cycles, the Mobile SDRAM is ready for normal opeartion.
Programming the registers
Mode Register
The mode register contains the specific mode of operation of the Mobile SDRAM. This register includes the selection of a burst length(1, 2, 4, 8, Full Page), a cas latency(2 or 3), a burst type. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command.
Extended Mode Register
The extended mode register contains the specific features of self refresh opeartion of the Mobile SDRAM. This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set command.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and the value on the A0-A11 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write opeartions can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the sarting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the CAS latency will be determined by the values programmed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Precharge
The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the precharge command is issued.
Auto Precharge
The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.
Burst Termination
The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open.
Data Mask
The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is issued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command is issued, data inputs can't be written with no clock delay. If data mask is initiated by asserting low on DQM during the read cycle, the data outputs are enabled. If DQM is asserted to High. the data outputs are masked (disabled) and become Hi-Z state after 2 cycle later. During the write cycle, DQM mask data input with zero latency
CK CM D W RIT
DM
Data M asking H i-Z D ata M asking
0 Latency
D 0D IN0 D 1 D0 MK D1 D 0DIN2 D 1
0 Latency
D0 MK D1
DQ
W rite D ata M asking
CK CMD READ
DM
D a ta M asking
2 Laten cy
H i-Z
DQ
D0 OUT0 1 D D
D 0 O U T1 1 D D
D0 DOT2 1 D D
D0 MK
D1
R ead D ata M askin g
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Clock Suspend
The Clock Suspend command is used to suspend the internal clock of Mobile SDRAM. The clock suspend operation stops transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation of the device. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations. (See examples in next Figures)
CLK Command CKE Internal CLK
Frozen Int. CLK by CKE (CKE = Fixed Low)
RD
Masked by CKE
DQ
Q1
Q2
Clock Suspend Mode
Q3
Q4
Command CKE
WR
Masked by CKE
Internal CLK
Frozen Int. CLK by CKE (CKE = Fixed Low)
DQ
D1
D2
D3
Clock Suspend Mode
D4
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Power Down
The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all of the input buffer except CKE are gated off.
Auto Refresh
The Auto Refresh command is used during normal operation and is similar to CBR refresh in Conventional DRAMs. This command must be issued each time a refresh is required. When an Auto Refresh command is issued , the address bits is ''Don't care'', because the specific address bits is generated by internal refresh address counter.
Self Refresh
The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these two modes.
Deep Power Down
The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. For more information, see the special operation for Low Power consumption of this data sheet.
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Special Operation for Low Power Consumption
Deep Power Down Mode
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. Full initialization is required when the device exits from Deep Power Down Mode.
Truth Table
Current State
Idle Deep Power Down
Command
Deep Power Down Entry Deep Power Down Exit
CKEn-1
H L
CKEn
L H
CS
L X
RAS
H X
CAS
H X
WE
L X
Deep Power Down Mode Entry
The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the clock, while CKE is low. The following diagram illustrates deep power down mode entry.
CKE
CS
RAS CAS
WE
tRP Pre-charge if needed
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Deep Power Down Entry
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
Deep Power Down Mode (Continued) Deep Power Down Mode Exit Sequence
The Deep Power Down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command.
1. Maintain NOP input conditions for a minimum of 200usec 2. Issue precharge commands for all banks of the device 3. Issue 8 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register
The following timing diagram illustrates deep power down mode exit sequence.
CLK CKE CS RAS CAS WE
200us
tRP
tRC
Deep Power Down Exit
All Banks Precharge
Auto Refresh
Auto Refresh
Mode Register Set
Extended Mode Register Set
New Command Accepted Here
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128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series
PACKAGE INFORMATION
54 Ball FBGA 0.8mm pitch (Size 8.0mm x 8.0mm, t=1.0mm max)
8.00 +/- 0.10 3.20 1.60 0.80
A1 INDEX MARK Unit [mm]
0.80 Typ.
8.00 +/- 0.10
Bottom View
0.45 +/- 0.05 0.34 +/- 0.05
0.80
1.375
0.80 Typ.
0.95 +0.05/-0.10
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